View ICS950813_180812.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Integrated Circuit Systems, Inc.
ICS950813
Advance Information
Frequency Generator with 200MHz Differential CPU Clocks
Recommended Application: CK-408 clock for Brookdale/Odem/Montara-GM for P4/Banias processor. Output Features: * 3 Differential CPU Clock Pairs @ 3.3V * 7 PCI (3.3V) @ 33.3MHz including 2 early PCI clocks * 3 PCI_F (3.3V) @ 33.3MHz * 1 USB (3.3V) @ 48MHz, 1 DOT (3.3V) @ 48MHz * 1 REF (3.3V) @ 14.318MHz * 5 3V66 (3.3V) @ 66.6MHz * 1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz Features: * Provides standard frequencies and additional 3%, 5% and 10% over-clocked frequencies * Supports spread spectrum modulation: No spread, Center Spread (0.3%, 0.55%), or Down Spread (-0.5%, -0.75%) * Offers adjustable PCI early clock via latch inputs * Selectable 1X or 2X strength for REF via I2C interface * Programmable group to group skew * Linear programmable frequency and spreading % * Efficient power management scheme through PD#, CPU_STOP# and PCI_STOP#. * Uses external 14.318MHz crystal * Stop clocks and functional control available through I2C interface. Key Specifications: * CPU Output Jitter <150ps * 3V66 Output Jitter <250ps * CPU Output Skew <100ps
Pin Configuration
VDDREF X1 X2 GND PCICLK_F0 PCICLK_F1 *ASEL/PCICLK_F2 VDDPCI GND PCICLK0 **E_PCICLK1/PCICLK1 PCICLK2 **E_PCICLK3/PCICLK3 VDDPCI GND PCICLK4 PCICLK5 PCICLK6 VDD3V66 GND 3V66_2 3V66_3 3V66_4 3V66_5 *PD# VDDA GND Vtt_PWRGD# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 REF FS1 FS0 CPU_STOP#* CPUCLKT0 CPUCLKC0 VDDCPU CPUCLKT1 CPUCLKC1 GND VDDCPU CPUCLKT2 CPUCLKC2 MULTSEL* IREF GND PWRSAVE#* 48MHz_USB/FS2** 48MHz_DOT VDD48 GND 3V66_1/VCH_CLK/FS3** PCI_STOP#* 3V66_0/FS4** VDD3V66 GND SCLK SDATA
56-Pin 300mil SSOP 56-Pin 240mil TSSOP
*
These inputs have 120K internal pull-up resistors to VDD. ** Internal pull-down resistors to ground.
Block Diagram
PLL2 48MHz_USB 48MHz_DOT
Functionality Table
FS1 0 FS0 0 1 0 1 CPU MHz 100.00 133.33 200.00 166.66 AGP MHz 66.67 66.67 66.67 66.66 PCI MHz 33.33 33.33 33.33 33.33
X1 X2
XTAL OSC 3V66 (5:2)
0 1 1
PLL1 Spread Spectrum PWRSAVE# Vtt_PWRGD# PD# CPU_STOP# PCI_STOP# MULTSEL FS (4:0) SDATA SCLK
0708--10/10/02
REF
CPU DIVDER Stop
3 3
CPUCLKT (2:0) CPUCLKC (2:0) PCICLK (6:0)
Asynchronous AGP/PCI Frequency Selection Table
Byte7 Bit5 Byte7 Bit4 0 0 0 1 1 0 1 1 AGP Frequency 66.00 75.43 88.00 -PCI Frequency 33.00 37.72 44.00 --
Control Logic
PCI DIVDER 3V66 DIVDER
Stop
7
PCICLK_F (2:0)
3
3V66_0 Config. Reg. 3V66_1/VCH_CLK I REF
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
ICS950813
ICS950813
Advance Information
Pin Description
PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 PIN NAME VDDREF X1 X2 GND PCICLK_F0 PCICLK_F1 *ASEL/PCICLK_F2 VDDPCI GND PCICLK0 **E_PCICLK1/PCICLK1 PCICLK2 **E_PCICLK3/PCICLK3 VDDPCI GND PCICLK4 PCICLK5 PCICLK6 VDD3V66 GND 3V66_2 3V66_3 3V66_4 3V66_5 *PD# VDDA GND Vtt_PWRGD# PIN TYPE PWR IN OUT PWR OUT OUT I/O PWR PWR OUT I/O OUT I/O PWR PWR OUT OUT OUT PWR PWR OUT OUT OUT OUT IN PWR PWR IN DESCRIPTION Ref, XTAL power supply, nominal 3.3V Crystal input,nominally 14.318MHz. Crystal output, Nominally 14.318MHz Ground pin. Free running PCI clock not affected by PCI_STOP# . Free running PCI clock not affected by PCI_STOP# . Asynchronous AGP/PCI frequency latch input pin / 3.3V PCI free running clock put. Pull-Up = Main PLL / Pull-Down = Async Fix PLL Power supply for PCI clocks, nominal 3.3V Ground pin. PCI clock output. Early/Normal PCI clock output latched at power up. PCI clock output. Early/Normal PCI clock output latched at power up. Power supply for PCI clocks, nominal 3.3V Ground pin. PCI clock output. PCI clock output. PCI clock output. Power pin for the 3V66 clocks. Ground pin. 3.3V 66.66MHz clock output 3.3V 66.66MHz clock output 3.3V 66.66MHz clock output 3.3V 66.66MHz clock output Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. 3.3V power for the PLL core. Ground pin. This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are valid and are ready to be sampled. This is an active low input.
0708--10/10/02
2
ICS950813
Advance Information
Pin Description (Continued)
PIN # 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 PIN NAME SDATA SCLK GND VDD3V66 3V66_0/FS4** PCI_STOP#* 3V66_1/VCH_CLK/FS3** GND VDD48 48MHz_DOT 48MHz_USB/FS2** PWRSAVE#* GND IREF MULTSEL* CPUCLKC2 CPUCLKT2 VDDCPU GND CPUCLKC1 CPUCLKT1 VDDCPU CPUCLKC0 CPUCLKT0 CPU_STOP#* FS0 FS1 REF PIN TYPE I/O IN PWR PWR I/O IN I/O PWR PWR OUT I/O IN PWR OUT IN OUT OUT PWR PWR OUT OUT PWR OUT OUT IN IN IN OUT DESCRIPTION Data pin for I2C circuitry 5V tolerant Clock pin of I2C circuitry 5V tolerant Ground pin. Power pin for the 3V66 clocks. Frequency select latch input pin / 3.3V 66.66MHz clock output. Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low Frequency select latch input pin / 3.3V 66.66MHz clock output / 48MHz VCH clock output. Ground pin. Power for 24 & 48MHz output buffers and fixed PLL core. 48MHz clock output. Frequency select latch input pin / 3.3V 48MHz clock output. Real Time input pin to change frequency to under-clock entries located in FS 4:2 = '100'. Clock groups gear ratio will not be change during this operation. Ground pin. This pin establishes the reference current for the CPUCLK pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 3.3V LVTTL input for selection the current multiplier for CPU outputs "Complementary" clocks of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. "True" clocks of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Supply for CPU clocks, 3.3V nominal Ground pin. "Complementary" clocks of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. "True" clocks of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Supply for CPU clocks, 3.3V nominal "Complementary" clocks of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. "True" clocks of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Stops all CPUCLK besides the free running clocks Frequency select pin. Frequency select pin. 14.318 MHz reference clock.
Power Supply
Pin Number VDD 1 37 46 GND 4 36 47 Description Xtal, Ref, CPU PLL, digital 48MHz, Fix Digital, Fix Analog Master clock, CPU Analog
0708--10/10/02
3
ICS950813
Advance Information
Frequency Select Table 1
Bit4 Bit3 Bit2 Bit1 Bit0 FS4 FS3 FS2 FS1 FS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU MHz 100.00 133.33 200.00 166.66 100.00 133.33 200.00 166.66 100.00 133.33 200.00 166.66 100.00 133.33 200.00 166.66 80.00 106.66 160.00 133.33 103.00 137.33 206.00 171.66 105.00 140.00 174.99 110.00 146.66 Test/2 183.33 AGP MHz 66.67 66.67 66.67 66.66 66.67 66.67 66.67 66.66 66.67 66.67 66.67 66.66 66.67 66.67 66.67 66.66 53.33 53.33 53.33 53.33 68.67 68.66 68.67 68.66 70.00 70.00 70.00 73.33 73.33 Test/4 73.33 PCI MHz 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 26.67 26.67 26.67 26.67 34.33 34.33 34.33 34.33 35.00 35.00 35.00 36.67 36.67 Test/8 36.67 Spread % 0.3% Center 0.3% Center 0.3% Center 0.3% Center 0 - 0.5% down 0 - 0.5% down 0 - 0.5% down 0 - 0.5% down 0.55% Center 0.55% Center 0.55% Center 0.55% Center 0 - 0.75% down 0 - 0.75% down 0 - 0.75% down 0 - 0.75% down Spread Off Spread Off Spread Off Spread Off 0.3% Center 0.3% Center 0.3% Center 0.3% Center 0.3% Center 0.3% Center N/A 0.3% Center 0.3% Center 0.3% Center N/A 0.3% Center
Tristate Tristate Tristate
0708--10/10/02
4
ICS950813
Advance Information
Host Swing Select Functions
MULTSEL 0 Board Target 50 ohms Reference R, Rr = 221 1%, Iref = 5.00mA Rr = 475 1%, Iref = 2.32mA Output Ioh = 4 * I REF Voh @ Z 1.0V @ 50 ohm
1
50 ohms
Ioh = 6 * I REF
0.7V @ 50 ohm
PCI Select Functions
E_PCICLK1 0 0 1 1 E_PCICLK3 0 1 0 1 E_PCICLK(3,1) * 0ns 0.5ns 1.0ns 1.5ns
Note:
E_PCICLK1 = 10Kohm resistor. E_PCICLK3 = 10Kohm resistor. 0 = No resistor
*
1 = 10Kohm pull-up to VDD. Approximate values
Frequency Select Table 2
Freqency Select FS4 0 0 0 0 1 1 1 1 FS3 0 0 1 1 0 0 1 1 FS2 0 1 0 1 0 1 0 1 CPU, 3V66, PCI Standard Clocking Clocking Mode 0.3% Center Spread
Standard Clocking 0 to -0.5%, Down Spread Standard Clocking 0.3% Center Spread Standard Clocking 0 to - 0.75%, Down Pwr Save Clocking Spread Off 3% Overclocking 0.3% Center Spread 5% Overclocking 0.3% Center Spread 10% Overclocking 0.3% Center Spread
PWRSAVE# Usage Illustration
PWRSAVE# = '1'. as PWRSAVE# is driven back to high '1'. The output frequencies will be driven back to the original programmed frequencies smoothly. Notice that this operation will only happen after the PWRSAVE# has been driven to '0'. This will not affect power up or I2C programmed frequencies if the PWRSAFE# has been tied to a '1'.
Bit4 FS4 X X X X 1 1 1 1 Bit3 FS3 X X X X 0 0 0 0 Bit2 FS2 X X X X 0 0 0 0 Bit1 FS1 0 0 1 1 0 0 1 1 Bit0 FS0 0 1 0 1 0 1 0 1 CPU MHz XXX XXX XXX XXX 80.00 106.66 160.00 133.33 AGP MHz XXX XXX XXX XXX 53.33 53.33 53.33 53.33 PCI MHz XXX XXX XXX XXX 26.67 26.67 26.67 26.67
PWRSAVE# = '0'. as PWRSAVE# is driven to low '0'. The output frequencies of the CPU, AGP and PCI clock will smoothly switch to frequencies indicated by FS (4:2) = 100. The frequencies gear ratio will be kept the same. Notice that the 48MHz & REF frequencies will not be changed. This function can be used with asynchronous AGP/PCI frequencies.
0708--10/10/02
5
ICS950813
Advance Information
BYTE 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
Pin # 35 53 34
Affected Pin Name Spread Enabled CPUCLKT(2:0) 3V66_1/VCH_CLK/FS3** CPU_STOP#* PCI_STOP#*
Control Function Spread Spectrum Control Power down mode output level 0= CPU driven in power down 1= undriven VCH/66.66 Select Reflects value of pin Reflects value of pin at power up. Also can be set. Frequency Selection Frequency Selection Frequency Selection
Type RW RW RW R RW RW R R
Bit Control 0 1 OFF ON HIGH 66.66 Stop Stop LOW 48.00 Active Active -
PWD 0 0 0 X X X X X
Bit 2 39 FS3 Bit 1 55 FS1 Bit 0 54 FS0 Note: For PCI_STOP# function, refer to table 3. BYTE 1 Bit 7 Affected Pin Name MULTSEL*
Reflects value of pin CPU_Stop mode output level Bit 6 CPUCLKT(2:0) 0= CPU driven when stopped 1 = undriven CPUCLKT2, CPUCLKC2 Allow control of output with Bit 5 45, 44 (see note) assertion of CPU_STOP#. CPUCLKT1, CPUCLKC1 Allow control of output with Bit 4 49, 48 (see note) assertion of CPU_STOP#. CPUCLKT0, CPUCLKC0 Allow control of output with Bit 3 52, 51 (see note) assertion of CPU_STOP#. Bit 2 45, 44 CPUCLKT2, CPUCLKC2 Output control Bit 1 49, 48 CPUCLKT1, CPUCLKC1 Output control Bit 0 52, 51 CPUCLKT0, CPUCLKC0 Output control Note: CPUCLK(2:0) can be turned on/off by CPU_STOP#. Refer to table 4. Affected Pin Control Function Name REF 1X or 2X Strength control PCICLK6 Output control PCICLK5 Output control PCICLK4 Output control **E_PCICLK3/PCICLK3 Output control PCICLK2 Output control **E_PCICLK1/PCICLK1 Output control PCICLK0 Output control can be turned on/off by PCI_STOP#. Refer to table 3.
Pin # 43
Control Function
Type R RW RW RW RW RW RW RW
Bit Control 0 1 HIGH Not Freerun Not Freerun Not Freerun Disable Disable Disable LOW Freerun Freerun Freerun Enable Enable Enable
PWD x 0 0 0 0 1 1 1
BYTE 2 Pin # Bit 7 56 Bit 6 18 Bit 5 17 Bit 4 16 Bit 3 13 Bit 2 12 Bit 1 11 Bit 0 10 Note: PCICLK(6:0)
Type RW RW RW RW RW RW RW RW
Bit Control 0 1 1X 2X Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable
PWD 0 1 1 1 1 1 1 1
0708--10/10/02
6
ICS950813
Advance Information
BYTE 3 Bit 7 Bit 6
Affected Pin Pin # 38 39 Name 48MHz_DOT 48MHz_USB/FS2**
Control Function
Type RW RW RW RW RW RW RW RW
Bit Control 0 Disable Disable Freerun Freerun Freerun Disable Disable Disable 1 Enable Enable Not Freerun Not Freerun Not Freerun Enable Enable Enable PWD 1 1 0 0 0 1 1 1
Output control Output control Allow control of output with Bit 5 7 *ASEL/PCICLK_F2 (see note) assertion of PCI_STOP#. Allow control of output with Bit 4 6 PCICLK_F1 (see note) assertion of PCI_STOP#. Allow control of output with Bit 3 5 PCICLK_F0 (see note) assertion of PCI_STOP#. Bit 2 7 *ASEL/PCICLK_F2 Output control Bit 1 6 PCICLK_F1 Output control Bit 0 5 PCICLK_F0 Output control Note: PCICLK_F(2:0) can be turned on/off by PCI_STOP#. Refer to table 5. BYTE 4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BYTE 5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Affected Pin Name FS3 FS4 3V66_0/FS4** 3V66_1/VCH_CLK/FS3** 3V66_5 3V66_4 3V66_3 3V66_2 Affected Pin Name PD Mode Iref Mirror Enable Reserved 3V66(5:2) (See table 6) 3V66(1:0) (See table 7) 48MHz_DOT Slew Control 48MHz_USB Slew Control Control Function Frequency Selection Frequency Selection Output control Output control Output control Output control Output control Output control
Pin # 35 33 33 35 24 23 22 21
Type RW RW RW RW RW RW RW RW
Bit Control 0 1 Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Bit Control 0 1 OFF Freerun Freerun ON Not Freerun Not Freerun -
PWD X X 1 1 1 1 1 1
Pin # X X X X 38 39
Control Function Allow Iref Mirror to be ON during Power Down Mode Reserved Allow control of output with assertion of CPU_STOP#. Allow control of output with assertion of CPU_STOP#. 00 = Medium (default), 01 = Low, 11,10 =High 00 = Medium (default), 01 = Low, 11,10 =High
Type RW X X X RW RW RW RW
PWD 0 0 0 0 0 0 0 0
Note: Functions in Byte 5 of CK408 were intended as a test and debug byte only. BYTE 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Affected Pin Name Revision ID Bit 3 Revision ID Bit 2 Revision ID Bit 1 Revision ID Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Bit Control 0 1 -
Pin # X X X X X X X X
Control Function Revision ID Value Based on Device Revision (Reserved) (Reserved) (Reserved) (Reserved)
Type R R R R R R R R
PWD 0 0 0 0 0 0 0 1
0708--10/10/02
7
ICS950813
Advance Information
BYTE 7 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin # X X X X X X X X
Affected Pin Name (Reserved) AEN AFS1 AFS0 (Reserved) (Reserved) (Reserved) (Reserved)
Control Function (Reserved) 3V66/PCI Freq Source Select Async Freq select bit 1 Async Freq select bit 0 (Reserved) (Reserved) (Reserved) (Reserved)
Type RW RW RW RW RW RW RW RW
Bit Control 0 1 Fix_PLL CPU_PLL Async Sync See Async Freq Selection Table -
PWD 1 1 0 0 1 1 1 1
BYTE 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Pin # X X X X X X X
Affected Pin Name -
Control Function (Reserved) (Reserved) (Reserved) (Reserved)
Type X X X X R R R
Readback Byte Count
Bit Control 0 1 -
PWD 0 0 0 0 1 1 1
Bit 0 X R 1 Note: Byte 8 is for ICS test only. Do not write as system damage may occur. Bit(2:0) contain the readback Byte count. BYTE 9 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Affected Pin Pin # 35 7, 6, 5 13, 12, 11, 10
111 8, 7, 6
Name VCHCLK Slew Control PCICLK_F (2:0) Slew Contol PCICLK (3:0) Slew Contol PCICLK (6:4) Slew Contol
Control Function 00 = High(default), 01 = Low, 11,10 = Medium 00 (default), 11 = Medium 01 = Low, 10 =High 00 (default), 11 = Medium 10 = Low, 01 =High 00 (default), 11 = Medium 10 = Low, 01 =High
Type RW RW RW RW RW RW RW RW
Bit Control 0 1 PWD 0 0 0 0 0 0 0 0
BYTE 10 Bit 7
Pin # X
Affected Pin Name -
Control Function M/N Enable (Enable access to Byte 11 - 14) Unused
Type RW RW RW -
Bit 6 X Bit 5 X 3V66 (5:2) Skew Approx 250ps per bit (Ref to PCI) Bit 4 X Bit 3 X Unused Bit 2 X Unused Bit 1 X Unused Bit 0 X Unused Note: See table 8 for Byte 11-14 default information
Bit Control 0 1 Byte HW/B0 (11-14) -
PWD 0 0 0 0 1 0 1 0
0708--10/10/02
8
ICS950813
Advance Information
BYTE Affected Pin Bit Control Control Function Type 11 Pin # Name 0 1 Bit 7 X VCO Divider Bit8 RW Bit 6 X REF Divider Bit6 RW Bit 5 X REF Divider Bit5 RW Bit 4 X REF Divider Bit4 RW Bit 3 X REF Divider Bit3 RW Bit 2 X REF Divider Bit2 RW Bit 1 X REF Divider Bit1 RW Bit 0 X REF Divider Bit0 RW Note: The decimal representation of these 7 bits (Byte 11 bit[6:0]) + 2 is equal to the REF divider value.
PWD X X X X X X X X
BYTE 12 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Affected Pin Pin # X X X X X X X X Name -
Control Function VCO VCO VCO VCO VCO VCO VCO VCO Divider Divider Divider Divider Divider Divider Divider Divider Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Type RW RW RW RW RW RW RW RW
Bit Control 0 1 PWD X X X X X X X X
Note: The decimal representation of these 9 bits (Byte 12 bit[7:0]) and Byte 11 bit [7]) + 8 is equal to the VCO divider value.
BYTE 13 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Affected Pin Pin # X X X X X X X X Name -
Control Function Spread Spectrum Bit7 Spread Spectrum Bit6 Spread Spectrum Bit5 Spread Spectrum Bit4 Spread Spectrum Bit3 Spread Spectrum Bit2 Spread Spectrum Bit1 Spread Spectrum Bit0
Type RW RW RW RW RW RW RW RW
Bit Control 0 1 PWD X X X X X X X X
Note: Please utilize software utility provided by ICS Application Engineering to configure spread spectrum. Incorrect spread percentage may cause system failure.
BYTE 14 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Affected Pin Pin # X X X X X X X X Name -
Control Function (Reserved) (Reserved) Spread Spectrum Bit13 Spread Spectrum Bit12 Spread Spectrum Bit11 Spread Spectrum Bit10 Spread Spectrum Bit9 Spread Spectrum Bit8
Type RW RW RW RW RW RW RW RW
Bit Control 0 1 PWD X X X X X X X X
Note: Please utilize software utility provided by ICS Application Engineering to configure spread spectrum. Incorrect spread percentage may cause system failure.
0708--10/10/02
9
ICS950813
Advance Information
Table 3 PCI_STOP# I2C Control Table PCI_STOP# (Pin 34) Byte 0 Bit 3 Write Bit Byte 0, Bit 3 Read Bit (Internal Status)
0 0 1 1 Note: When this Byte 0, Bit 3 is
0 0 1 0 0 0 1 1 low (0), all PCI clocks are stopped.
Table 4 CPUCLKT/C (2:0) Outputs I2C Control Table CPU_STOP# Byte 1 CPUCLKT/C (2:0) Outputs (Pin 53) Bit 3, 4, 5 0 0 Stop 0 1 Running 1 0 Running 1 1 Running Individual CPUCLK outputs are controlled by Byte 1, Bit 3, 4, and 5. Note: Table 5 PCICLK_F (2:0) Outputs I2C Control Table PCI_STOP# Byte 3 PCICLK (2:0) Outputs (Pin 34) Bit 3, 4, 5 0 0 Stop 0 1 Running 1 0 Running 1 1 Running Individual PCICLK outputs are controlled by Byte 3, Bit 3, 4, and 5. Note: Table 6 3V66 (5:2) I2C Control Table CPU_STOP# (Pin 53) Byte 5 Bit 5 3V66 (5:2)
0 0 Running 0 1 Stopped 1 0 Running 1 1 Running Note: Activating Byte 5, Bit 5 will allow CPU_STOP# to control stop of pins 21, 22, 23, and 24. Table 7 3V66 (1:0) I2C Control Table CPU_STOP# Byte 5 3V66 (1:0) (Pin 53) Bit 4 0 0 Running 0 1 Stopped 1 0 Running 1 1 Running Note: Activating Byte 5, Bit 4 will allow CPU_STOP# to control stop of pins 33 and 35.
0708--10/10/02
10
ICS950813
Advance Information
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD + 0.5 V Ambient Operating Temperature . . . . . . . . . . 0C to +90C Case Temperature . . . . . . . . . . . . . . . . . . . . . . 115C Storage Temperature . . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current IIL2 Operating Supply Current IDD3.3OP IDD3.3OP Powerdown Current Input Frequency Pin Inductance Input Capacitance1 PWRSAVE Stabilization1,2 Clk Stabilization1,2 Delay 1
1 2
SYMBOL CONDITIONS MIN VIH 2 VIL VSS - 0.3 IIH VIN = VDD -5 IIL1 VIN = 0 V; Inputs with no pull-up resistors -5 VIN = 0 V; Inputs with pull-up resistors CL = Full load; Select @ 100 MHz CL =Full load; Select @ 133 MHz IREF=5 mA VDD = 3.3 V Logic Inputs Output pin capacitance X1 & X2 pins From Assertion of PWRSAVE# to 1st clock. From PowerUp or deassertion of PowerDown to 1st clock. Output enable delay (all outputs) Output disable delay (all outputs) -200 229 220
TYP
MAX VDD + 0.3 0.8 5
UNITS V V mA mA
280 280 45 7 5 6 33 1.8 1.8
mA mA mA MHz nH pF pF pF ms ms ns ns
IDD3.3PD Fi Lpin CIN COUT CINX TPWRSV TSTAB tPZH,tPZL tPHZ,tPLZ
27
30
1 1
10 10
Guaranteed by design, not 100% tested in production. See timing diagrams for buffered and un-buffered timing requirements.
0708--10/10/02
11
ICS950813
Advance Information
Electrical Characteristics - CPUCLKT/C
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Current Source Output VO = Vx Zo1 Impedance I OH = -1 mA Output High Voltage V OH3 I OL = 1 mA Output Low Voltage VOL3 Voltage High VHigh Statistical measurement on single ended Voltage Low VLow signal using oscilloscope math function. Max Voltage Vovs Measurement on single ended signal Min Voltage Vuds using absolute value. Crossing Voltage (abs) Vcross(abs) Crossing Voltage (var) d-Vcross Variation of crossing over all edges Rise Time tr V OL = 0.175V, V OH = 0.525V Fall Time tf V OH = 0.525V V OL = 0.175V Rise Time Variation d-tr Fall Time Variation d-tf Duty Cycle Skew Jitter, Cycle to cycle
1
MIN 3000 2.4 660 -150 -450 250 175 175
TYP
MAX
UNITS V
0.4 850 150 1150 550 140 700 700 125 125 55 100 150
mV mV mV mV ps ps ps ps % ps ps
dt3 tsk3 t jcyc-cyc
1
Measurement from differential wavefrom V T = 50% V T = 50%
45
Guaranteed by design, not 100% tested in production. 2 I OWT can be varied and is selectable thru the MULTSEL pin.
Electrical Characteristics - 3V66
TA = 0 - 70C; V DD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER Output Frequency Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL FO1 RDSP11 V OH1 V OL1 I OH1 IOL1 t r11 t f11 dt11 t sk11 t jcyc-cyc
1
CONDITIONS V O = VDD*(0.5) I OH = -1 mA I OL = 1 mA V OH@MIN = 1.0 V, V OH@MAX = 3.135 V V OL @MIN = 1.95 V, V OL @MAX = 0.4 V V OL = 0.4 V, V OH = 2.4 V V OH = 2.4 V, V OL = 0.4 V V T = 1.5 V V T = 1.5 V V T = 1.5 V 3V66
MIN 12 2.4 -33 30 0.5 0.5 45
TYP
MAX 55 0.55 -33 38 2 2 55 250 250
UNITS MHz V V mA mA ns ns % ps ps
Guaranteed by design, not 100% tested in production.
0708--10/10/02
12
ICS950813
Advance Information
Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER Output Frequency Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter,cycle to cyc
1
SYMBOL FO1 RDSP11 VOH1 VOL1 IOH1 I OL1 t r11 t f11 dt11 t sk11 tjcyc-cyc
1
CONDITIONS VO = V DD*(0.5) I OH = -1 mA I OL = 1 mA V OH@MIN = 1.0 V, V OH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 12 2.4 -33 30 0.5 0.5 45
TYP
MAX 55 0.55 -33 38 2 2 55 500 250
UNITS MHz V V mA mA ns ns % ps ps
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - VCH, 48MHz DOT, 48MHz, USB
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Frequency FO1 VO = VDD*(0.5) Output Impedance RDSP11 Output High Voltage Output Low Voltage Output High Current Output Low Current 48DOT Rise Time 48DOT Fall Time VCH 48 USB Rise Time VCH 48 USB Fall Time 48 DOT Duty Cycle VCH 48 USB Duty Cycle 48 DOT Jitter USB to DOT Skew VCH Jitter
1
MIN 20 2.4
TYP
MAX 60 0.4
UNITS MHz V V mA mA ns ns ns ns % % ps ns ps
VOH1 VOL1 IOH1 IOL1 t r11 t f11 t r11 t f11 dt11 dt11 tjcyc-cyc 1 t sk1
1 1
I OH = -1 mA I OL = 1 mA V
OH@MIN = 1.0 V, V OH@MAX
= 3.135 V
-29 29 0.5 0.5 1 1 45 45
-23 27 1 1 2 2 55 55 350 1 350
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V (0 OR 180 degrees) VT = 1.5 V
tjcyc-cyc
Guaranteed by design, not 100% tested in production.
0708--10/10/02
13
ICS950813
Advance Information
Electrical Characteristics - REF
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER Output Frequency Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter
1
SYMBOL FO1 RDSP11 VOH1 VOL1 IOH1 IOL1 tr11 tf11 dt11 tjcyc-cyc
1
CONDITIONS VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA V OH@MIN = 1.0 V, V OH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, V OL = 0.4 V VT = 1.5 V VT = 1.5 V
MIN 20 2.4 -29 29 1 1 45
TYP
MAX UNITS MHz 60 0.4 -23 27 2 2 55 1000 V V mA mA ns ns % ps
Guaranteed by design, not 100% tested in production.
0708--10/10/02
14
ICS950813
Advance Information
General I2C serial interface information How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * * * * * * * Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) starT bit Slave Address D2(H) WR WRite T Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
Index Block Read Operation
Controller (Host) T starT bit Slave Address D2(H) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
ACK
ACK
Byte N + X - 1 ACK P stoP bit
Byte N + X - 1 N P
0708--10/10/02
Not acknowledge stoP bit
15
ICS950813
Advance Information
Un-Buffered Mode 3V66 & PCI Phase Relationship All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock, there is no defined phase relationship between 3V66_1_VCH and other 3V66 clocks. The PCI group should lag 3V66 by the standard skew described below as Tpci.
3V66 (1:0) 3V66 (4:2) 3V66_5 PCICLK_F (2:0) PCICLK (6:0) E_PCICLK (3,1) Tepci Tpci
Group to Group Skews at Common Transition Edges: Unbuffered Mode
GROUP 3V66 to PCI1,2
1 2
SYMBOL S3V66-PCI
CONDITIONS 3V66 (5:0) leads 33MHz PCI
MIN 1.5
TYP 2.55
MAX 3.5
UNITS ns
Guarenteed by design, not 100% tested in production. 500ps Tolerance
E_PCICLK to PCICLK Skews
GROUP SYMBOL TE_PCI-PCI1 E_PCICLK to PCICLK 1 TE_PCI-PCI2 TE_PCI-PCI3
1
CONDITIONS E_PCICLK1 (pin 11)=0 E_PCICLK3 (pin 13)=1 E_PCICLK1 (pin 11)=1 E_PCICLK3 (pin 13)=0 E_PCICLK1 (pin 11)=1 E_PCICLK3 (pin 13)=1
MIN 0.3 0.8 1.3
TYP 0.5 1.0 1.5
MAX 0.7 1.2 1.7
UNITS ns ns ns
Guaranteed by design, not 100% tested in production.
0708--10/10/02
16
ICS950813
Advance Information
PCI_STOP# - Assertion (transition from logic "1" to logic "0") The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will latch low in their next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising edge. Assertion of PCI_STOP# Waveforms
PCI_STOP# PCI_F[2:0] 33MHz PCI[6:0] 33MHz
tsu
CPU_STOP# - Assertion (transition from logic "1" to logic "0") The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I2C configuration to be stoppable via assertion of CPU_STOP# are to be stopped after their next transition. When the I2C Bit 6 of Byte 1 is programmed to '0' the final state of the stopped CPU signals is CPU = High and CPU# = Low. There is to be no change to the output drive current values. The CPU will be driven high with a current value equal to (Mult 0 'select') x (Iref), the CPU# signal will not be driven . When the I2C Bit 6 of Byte 1 is programmed to '1' then final state of the stopped CPU signals is Low, both CPU and CPU# outputs will not be driven. Assertion of CPU_STOP# Waveforms
CPU_STOP# CPUCLKT CPUCLKC
CPU_STOP# Functionality
CPU_STOP# 1 0
CPUT Normal iref * Mult
CPUC Normal Float
0708--10/10/02
17
ICS950813
Advance Information
CPU_STOP# - De-assertion (transition from logic "0" to logic "1") All CPU outputs that were stopped are to resume normal operation in a glitch free manner. The maximum latency from the de-assertion to active outputs is to be defined to be between 2 - 6 CPU clock periods (2 clocks are shown). If the I2C Bit 6 of Byte 1 is programmed to "1" then the stopped CPU outputs will be driven High within 10 nS of CPU_Stop# deassertion.
De-assertion of CPU_STOP# Waveforms
CPU_STOP# CPUCLKT(2:0) Tdrive_CPU_STOP# <10ns @ 200mV *CPUCLKT(2:0)TS CPUCLKC(2:0) *Signal TS is CPUCLKT in Tri-State mode
PD# - Assertion (transition from logic "1" to logic "0") When PWRDWN# is sampled low by two consecutive rising edges of CPU clock, then all clock outputs except CPU clocks must be held low on their next high to low transitions. When the I2C Bit 6 of Byte 0 is programmed to '0' CPU clocks must be held with the CPU clock pin driven high with a value of 2 x Iref, and CPU# undriven. If Bit 6 of Byte 0 is '1' then both CPU and CPU# are undriven. Note the example below shows CPU = 133 MHz and Bit 6 of Byte 0 = '0', this diagram and description is applicable for all valid CPU frequencies 66, 100, 133, 200 MHz. Due to the state if the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete. Power Down Assertion of Waveforms
0ns PD# CPUCLKT 100MHz CPUCLKC 100MHz 3V66MHz PCICLK 33MHz USB 48MHz REF 14.318MHz 25ns 50ns
PD# Functionality
PD# 1 0
0708--10/10/02
CPUCLKT Normal iref * Mult
CPUCLKC Normal Float
3V66 66MHz Low
PCICLK_F PCICLK
33MHz
USB/DOT 48MHz 48MHz Low
Low
18
ICS950813
Advance Information
Power Down De-Assertion Mode The power-up latency needs to be less than 1.8mS. this is the time from the de-asseration of the powerdown of the ramping of the power supply until the time that stable clocks are output from the clock chip. If the I2C Bit 6 of Byte 0 is programmed to "1" then the stopped CPU outputs will be driven high within 3 nS of PD# de-asseration.
Test Configuration Diagram
Rs=33 Ohms 5% TLA
CLK408
Rs=33 Ohms 5% TLB
CPUCLKT test point
Rp=49.9 Ohms 1% Rset=475 Ohms 1%
Rp=49.9 Ohms 1% 2pF 5% 2pF 5%
CPUCLKC test point
MULTSEL Pin must be High
CPU 0.7V Configuration test load board termination
0708--10/10/02
19
ICS950813
Advance Information
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad 2K W
Via to VDD
8.2K W Clock trace to load Series Term. Res.
Fig. 1
0708--10/10/02
20
ICS950813
Advance Information
N
c
L
INDEX AREA
E1
E
12 D h x 45
a
A A1
In Millimeters SYMBOL COMMON DIMENSIONS MIN MAX A 2.41 2.80 A1 0.20 0.40 b 0.20 0.34 c 0.13 0.25 D SEE VARIATIONS E 10.03 10.68 E1 7.40 7.60 e 0.635 BASIC h 0.38 0.64 L 0.50 1.02 N SEE VARIATIONS 0 8 VARIATIONS N 56
10-0034
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
-Ce
b SEATING PLANE .10 (.004) C
D mm. MIN 18.31 MAX 18.55 MIN .720
D (inch) MAX .730
Reference Doc.: JEDEC Publication 95, M O-1 18
300 mil SSOP Package
Ordering Information
ICS950813yFT
Example:
ICS95 XXXX y F - T
Designation for tape and reel packaging Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
0708--10/10/02
21
ICS950813
Advance Information
N
c
L
INDEX AREA
E1
E
12 D
a
A2 A1
A
In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 D SEE VARIATIONS SEE VARIATIONS E 8.10 BASIC 0.319 BASIC E1 6.00 6.20 .236 .244 e 0.50 BASIC 0.020 BASIC L 0.45 0.75 .018 .030 N SEE VARIATIONS SEE VARIATIONS a 0 8 0 8 aaa -0.10 -.004 VARIATIONS
-Ce
b SEATING PLANE
N 56
10-0039
D mm. MIN MAX 13.90 14.10
D (inch) MIN .547 MAX .555
aaa C
Reference Doc.: JEDEC Publication 95, M O-153
(240 mil)
6.10 mm. Body, 0.50 mm. pitch TSSOP (20 mil)
Ordering Information
ICS950813yGT
Example:
ICS95 XXXX y G - T
Designation for tape and reel packaging Package Type G=TSSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS, AV = Standard Device
0708--10/10/02
22

▲Up To Search▲

Price & Availability of ICS950813

	To Download ICS950813 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .